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Churn
Issues
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_TV\v\Sdram_PLL_sim\cadence\ncsim_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_TV\Sdram_Control_4Port\Sdram_PLL_sim\synopsys\vcsmx\vcsmx_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_TV\Sdram_Control_4Port\Sdram_PLL_sim\synopsys\vcs\vcs_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_SDRAM_RTL_Test\v\pll_sim\synopsys\vcsmx\vcsmx_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_TV\Sdram_Control_4Port\Sdram_PLL_sim\cadence\ncsim_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_SDRAM_RTL_Test\v\pll_sim\synopsys\vcs\vcs_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_SDRAM_RTL_Test\Sdram_Control\sdram_pll0_sim\cadence\ncsim_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_SDRAM_RTL_Test\Sdram_Control\sdram_pll0_sim\synopsys\vcs\vcs_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_SDRAM_RTL_Test\Sdram_Control\sdram_pll0_sim\synopsys\vcsmx\vcsmx_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_Default\V\VGA_Audio_sim\cadence\ncsim_setup.sh
 1 3
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DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_SDRAM_RTL_Test\v\pll_sim\cadence\ncsim_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_Default\V\VGA_Audio_sim\synopsys\vcsmx\vcsmx_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_TV\v\Sdram_PLL_sim\synopsys\vcsmx\vcsmx_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\DE1_SoC_Default\V\VGA_Audio_sim\synopsys\vcs\vcs_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\SOC_FPGA\DE1_SOC_Linux_FB\vga_pll_sim\synopsys\vcsmx\vcsmx_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\SOC_FPGA\DE1_SOC_Linux_FB\vga_pll_sim\synopsys\vcs\vcs_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\SOC_FPGA\DE1_SOC_Linux_FB\vga_pll_sim\cadence\ncsim_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\ControlPanel\ControlPanel_QT\tab_gsensor.cpp
4 1 3
A
DE1-SoC CD\Demonstrations\FPGA\my_first_fpga\pll_sim\cadence\ncsim_setup.sh
 1 3
A
DE1-SoC CD\Demonstrations\FPGA\my_first_fpga\pll_sim\synopsys\vcs\vcs_setup.sh
 1 3