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chipyard
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Grade
Name
Complexity
Churn
Issues
A
generators\chipyard\src\main\scala\clocking\FakePLL.scala
 1 2
A
generators\chipyard\src\main\scala\clocking\DividerOnlyClockGenerator.scala
10 6 1
A
generators\chipyard\src\main\scala\clocking\ClockGroupNamePrefixer.scala
8 3 -
A
generators\chipyard\src\main\scala\clocking\ClockGroupCombiner.scala
1 4 -
A
generators\chipyard\src\main\scala\clocking\ClockDividerN.scala
1 1 -
A
generators\chipyard\src\main\scala\clocking\ClockBinders.scala
 10 -
A
generators\chipyard\src\main\scala\TestSuites.scala
23 3 1
A
generators\chipyard\src\main\scala\System.scala
 3 -
A
generators\chipyard\src\main\scala\Subsystem.scala
6 9 -
A
generators\chipyard\src\main\scala\SpikeTile.scala
7 7 -
A
generators\chipyard\src\main\scala\Generator.scala
 1 -
A
generators\chipyard\src\main\scala\DigitalTop.scala
 5 -
A
generators\chipyard\src\main\scala\ConfigFinder.scala
2 2 -
A
generators\chipyard\src\main\scala\ChipTop.scala
 4 -
A
generators\chipyard\src\main\resources\csrc\spiketile.cc
228 5 7
A
fpga\src\main\scala\vcu118\bringup\TestHarness.scala
 3 -
A
fpga\src\main\scala\vcu118\bringup\IOBinders.scala
 3 -
A
fpga\src\main\scala\vcu118\bringup\HarnessBinders.scala
 4 -
A
fpga\src\main\scala\vcu118\bringup\DigitalTop.scala
 2 -
A
fpga\src\main\scala\vcu118\bringup\CustomOverlays.scala
7 2 1