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chipyard
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Name
Complexity
Churn
Issues
A
fpga\src\main\resources\vcu118\sdboot\include\sections.h
0 1 -
A
fpga\src\main\resources\vcu118\sdboot\common.h
0 1 -
A
.github\scripts\run-tests.sh
 13 1
A
fpga\src\main\scala\vcu118\bringup\HarnessBinders.scala
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A
generators\chipyard\src\main\scala\config\ChipConfigs.scala
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fpga\src\main\scala\vcu118\bringup\TestHarness.scala
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.github\workflows\chipyard-full-flow.yml
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A
generators\chipyard\src\main\scala\ChipTop.scala
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fpga\src\main\resources\vcu118\sdboot\include\devices\uart.h
0 1 -
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generators\chipyard\src\main\scala\DigitalTop.scala
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A
fpga\src\main\resources\vcu118\sdboot\include\devices\gpio.h
0 1 -
A
fpga\src\main\resources\vcu118\sdboot\include\devices\plic.h
0 1 -
A
generators\chipyard\src\main\scala\config\HeteroConfigs.scala
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generators\chipyard\src\main\scala\config\NoCoreConfigs.scala
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generators\chipyard\src\main\scala\config\NoCConfigs.scala
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generators\chipyard\src\main\scala\config\CVA6Configs.scala
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generators\chipyard\src\main\scala\config\AbstractConfig.scala
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generators\chipyard\src\main\scala\clocking\TLClockSelector.scala
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A
.github\workflows\require-label.yml
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.github\actions\git-workaround\action.yml
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