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chipyard
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Name
Complexity
Churn
Issues
A
generators\chipyard\src\main\scala\Subsystem.scala
6 9 -
A
fpga\src\main\scala\vcu118\Configs.scala
 9 1
A
fpga\src\main\scala\vc707\TestHarness.scala
5 9 -
A
generators\chipyard\src\main\scala\example\FlatTestHarness.scala
 9 -
A
scripts\init-submodules-no-riscv-tools-nolog.sh
 9 3
A
fpga\src\main\scala\arty\TestHarness.scala
4 9 -
A
generators\chipyard\src\main\scala\clocking\HasChipyardPRCI.scala
3 9 1
A
generators\chipyard\src\main\scala\config\PeripheralDeviceConfigs.scala
 8 -
A
fpga\src\main\scala\arty100t\HarnessBinders.scala
 8 -
A
generators\chipyard\src\main\scala\clocking\TileClockGater.scala
 8 1
A
generators\chipyard\src\main\scala\config\TracegenConfigs.scala
 7 -
A
generators\chipyard\src\main\scala\SpikeTile.scala
7 7 -
A
generators\chipyard\src\main\scala\clocking\TileResetSetter.scala
 7 1
A
fpga\src\main\scala\arty\Configs.scala
 7 -
A
fpga\src\main\scala\arty100t\Harness.scala
5 7 -
A
fpga\src\main\scala\vc707\Configs.scala
 6 1
A
generators\chipyard\src\main\scala\config\fragments\ClockingFragments.scala
 6 -
A
generators\chipyard\src\main\scala\config\MMIOAcceleratorConfigs.scala
 6 2
A
generators\chipyard\src\main\scala\clocking\DividerOnlyClockGenerator.scala
10 6 1
A
generators\chipyard\src\main\scala\config\SpikeConfigs.scala
 6 -